Is it possible for a space smaller than a hydrogen atom to jeopardize the creation of the next generation of chips? This is the alarming lesson of a newly published study conducted by researchers from TU Wien. Instead of chasing a miracle semiconductor, it redirects attention to the less glamorous task of developing a functional interface between the atomically thin channel and its dielectric layer. Materials like graphene, MoS2, and WSe2 have been considered as potential successors to silicon due to their ability to preserve electrical properties at very thin dimensions, when silicon starts failing. However, according to the new finding, thin materials alone cannot solve any problems. A transistor will function properly only when its gate can efficiently control the flow of current in the channel, which does not occur when even an ultramicroscopically tiny gap appears between them.
What makes things difficult for advanced chips is an atomic gap between the active layer and dielectric film of 0.14 nm. The researchers discovered that many 2D semiconductors combined with oxide dielectrics produce weak van der Waals bonding between them, thus forming a gap. “In many combinations of 2D materials and insulating layers, the bonding between them is relatively weak” explains Prof. Tibor Grasser. Hence, a material which seems promising in isolation becomes less useful once integrated into an actual device structure.
Such findings are highly relevant due to the general trend in advanced chip development. Today, a broad roadmap of chip design includes a shift towards stacked architectures, with complementary FETs and monolithic 3D technology. The reason why ultrathin channels are used in them is that, on the one hand, they are easy to manufacture at low temperatures up to 400 ºC, while on the other hand, they are easily integrated. However, this combination is achieved precisely because of the dangling-bond-free nature of the semiconductor surface, which leads to poor interfacial adhesion.
The practical challenges of such integration can be already seen by analyzing the history of successful demonstrations in the manufacturing process. Transfer-based assembling of layers often causes residue formation, wrinkles, and partial lifting of the 2D film. Industry reports have pointed out cases of poor performance due to the impact of the transfer procedure, and recent technical overviews highlight the strong correlation of contact resistance, dielectric uniformity, and interfacial adhesion as the main bottlenecks in chip production. Consequently, no matter how well a material can be utilized, its performance becomes questionable once surrounded with other layers.
This is where the solution proposed by TU Wien stands out. Instead of optimizing each material separately, scientists suggest combining them in so-called “zipper materials.” “If the semiconductor industry wants to succeed with 2D materials, the active layer and the insulating layer must be designed together from the very beginning,” says Prof. Mahdi Pourfath. In other words, future chip design should include careful co-design of the interlayer interactions as well as of the active material itself.
In recent years, 2D transistors became the topic of extensive studies, whose results can be summarized as follows. Progress in chip manufacturing should focus on co-development of 2D semiconductors, contacting, oxide nucleation techniques, thermal management, and interconnections. The latter is especially important, as even thermal analysis began pointing out thermal boundary resistance as a consequence of weak interfacial bonding. Thus, the emergence of an interface gap is not only a geometrical but also technological challenge, which future scaling can face. “Our work is good news for the semiconductor industry,” Grasser said. “We can predict which materials are suitable for future miniaturization steps and which are not.”